9.12 System Interface Error Protection and Handling
Error Handling
This section describes error handling on the system command bus, system address/data bus, system state bus, and system response bus.
The 12-bit wide system command bus, SysCmd(11:0), is protected by odd parity.
Whenever the processor is in master state and it asserts SysVal* to indicate that it is driving valid information on the SysCmd(11:0) bus, it also drives odd parity on the SysCmdPar signal.
Whenever the processor is in slave state and an external agent asserts SysVal* to indicate that it is driving valid information on the SysCmd(11:0) bus, the processor checks the SysCmdPar signal for odd parity. If a parity error is detected, the processor ignores the SysCmd(11:0) and SysAD(63:0) buses for one SysClk cycle. The System interface unit posts a Cache Error exception and sets the SC bit in the local CacheErr register. Additionally, the processor informs the external agent by asserting SysUncErr* for one SysClk cycle. (See page 168 in Errata.)
Caution: By ignoring the SysCmd(11:0) and SysAD(63:0) buses, the processor to become unsynchronized with other processors or the external agent on the cluster bus.
SysAD(63:0) Bus
The 64-bit wide system address/data bus, SysAD(63:0), is protected by an 8-bit-wide ECC.
Whenever the processor is in master state and it asserts SysVal* to indicate it is driving valid information on the SysAD(63:0) bus, it also drives the proper ECC on the SysADChk(7:0) bus.
Whenever the processor is in slave state, error checking is enabled with the assertion of SysCmd(0), and an external agent asserts SysVal* to indicate it is driving valid information on the SysAD(63:0) bus, the processor checks the SysADChk(7:0) bus for the proper ECC.
If a correctable error is detected during an external address cycle, or during an external data cycle for a processor read or upgrade request originated by the R10000 processor, correction is automatically performed in-line without affecting latency. The processor asserts SysCorErr* for one SysClk cycle to inform the external agent that a correctable error has been detected and corrected.
If an uncorrectable error is detected during an external address cycle, the processor ignores the SysCmd(11:0) and SysAD(63:0) buses for one SysClk cycle, and the System interface unit posts a Cache Error exception and sets the SA bit in the local CacheErr register. Additionally, the processor informs the external agent by asserting SysUncErr* for one SysClk cycle. (See page 169 in Errata.)
Caution: By ignoring the SysCmd(11:0) and SysAD(63:0) buses, this processor may become unsynchronized with other processors or the external agent on the cluster bus.
If an uncorrectable error is detected or the data quality indication on SysCmd(5) is asserted during an external data cycle for a processor read or upgrade request originated by the processor, the R10000 asserts the corresponding incoming buffer uncorrectable error flag.
When the processor forwards block data from an incoming buffer entry after receiving an external ACK completion response, the associated incoming buffer uncorrectable error flags are checked, and if any are asserted, the System interface unit posts a single Cache Error exception and initializes the EE, D, and SIdx fields in the local CacheErr register.
When the processor forwards double/single/partial-word data from an incoming buffer entry after receiving an external ACK completion response, the associated incoming buffer uncorrectable error flag is checked and, if asserted, the System interface unit posts a Bus Error exception.
Table 9-8 presents the ECC matrix for the System interface address/data bus. This ECC matrix is identical to that used by the R4X00 System interface.
Table 9-8 ECC Matrix for System Interface Address/Data Bus
The 3-bit wide system state bus, SysState(2:0), is protected by odd parity. The processor drives odd parity on the SysStatePar signal.
The 5-bit wide system response bus, SysResp(4:0), is protected by odd parity.
Whenever an external agent asserts SysRespVal* to indicate it is driving valid information on the SysResp(4:0) bus, the processor checks the SysRespPar signal for odd parity. If a parity error is detected, the processor ignores the SysResp(4:0) bus for one SysClk cycle. The System interface unit posts a Cache Error exception and sets the SR bit in the local CacheErr register. Additionally, the processor informs the external agent by asserting SysUncErr* for one SysClk cycle. (See page 170 in Errata.)
Caution: If the processor ignores the SysResp(4:0) bus, it may become unsynchronized with other processors or the external agent on the cluster bus. Also, the processor will "hang" if a parity error is detected on the SysResp[4:0] bus during an external completion response cycle for a processor double/single/partial-word read request originated by the processor. The external agent may initiate a Soft Reset sequence to obtain the contents of the CacheErr register, and the CacheErr register will indicate a System interface uncorrectable system response bus error.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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